Author | Turino, Jon L. author |
---|---|
Title | Design to Test [electronic resource] : A Definitive Guide for Electronic Design, Manufacture, and Service / by Jon L. Turino |
Imprint | Dordrecht : Springer Netherlands, 1990 |
Edition | Second Edition |
Connect to | http://dx.doi.org/10.1007/978-94-011-6044-5 |
Descript | XXII, 368 p. online resource |
1 Introduction -- How (and Why) Circuits Are Tested -- Key Testability Techniques -- Testability Definitions -- Why Is Testability Important? -- Testability Awareness -- Testability Commitment -- Testability Benefits -- Testability Trends for the Future -- Design-to-Test Overview -- 2 System Level Guidelines -- System Analysis -- System Level Testability Guidelines -- 3 General Digital Circuit Guidelines -- Initialization -- Asynchronous Circuits and One-Shots -- Interfaces -- Built-in Test Diagnostics -- Feedback Loops -- Oscillators and Clocks -- Fan-in and Fan-out Considerations -- Bussed Logic -- Buffers -- Visibility Points -- Partitioning Functions into Logically Separable Units -- Wired OR/AND Functions -- Counters and Shift Registers -- Additional General Digital Board Guidelines -- Guidelines for Programmable Logic Devices -- 4 General Analog Circuit Guidelines -- General Analog Testability Guidelines -- Analog Circuit Elements -- Frequency Considerations -- High-Frequency Analog Circuits 81 Additional General Analog Circuit Guidelines -- Testability Guidelines for Hybrid Circuits -- 5 LSI/VLSI Board Level Guidelines -- LSI/VLSI Board Advantages and Disadvantages -- Partitioning of LSI/VLSI-Based Boards -- Controllability of LSI/VLSI-Based Boards -- Visibility on LSI/VLSI-Based Boards -- Initialization -- Synchronization -- Self-Tests -- Device Standardization -- Summary of LSI/VLSI Board Guidelines -- 6 Merchant Devices on Boards -- General Guidelines Using Merchant Devices -- The 8080A Microprocessor Family -- The 8085A Microprocessor Family -- The 8048 Microprocessor Family -- The 8086 Microprocessor Family -- The 80186 Processor -- The 80286 Processor -- The 80386 Processor -- The Z80 Microprocessor Family -- The Z8000 Microprocessor Family -- The 6800 Microprocessor Family -- The 2901 Microprocessor Family -- The 68000 Processor Family -- The 68020 Processor -- The 68030 Processor -- The 88000 RISC Processor Family -- The 320C2x DSP Device Family -- Merchant Semiconductor Use Guidelines Summary -- 7 LSI/VLSI ASIC Level Techniques -- Level Sensitive Scan Design (LSSD) -- Scan Path -- Scan/Set Logic -- Random Access Scan 169 Built-in Logic Block Observation (BILBO) -- Signature Analysis -- Reduced Intrusion Scan Path (RISP) -- Using Device Scan Paths for Board Level Testing -- Cross Check Technology Embedded Testability -- 8 Boundary Scan -- Board Test Problems as a Basis for Boundary Scan -- Boundary Scan Description -- Test Access Port Description -- Boundary Scan TAP Interconnection and Operation -- Types of Tests Using Boundary Scan -- Boundary Scan Cell Designs -- 9 Built-in Test (BIT) Approaches -- BIT Implementation Requirements -- BIT Access Bus Alternatives -- Chip Level BIT Implementations -- Dual-Port BIT Bus Implementations -- Built-in Test and Human Interactions -- Real-Time On-line Monitoring -- 10 Testability Busses -- The Proposed IEEE Standard Testability Bus -- Testability Busses and LSSD -- Testability Busses and Boundary Scan -- Testability Busses and Scan/Set -- TM and E-TM Testability Busses -- Testability Busses and the TAP -- Real-Time Testability Busses and Multiplexing -- Combination Serial/Real-Time Testability Bus -- Analog Testability Bus Implementation -- Testability Bus Configuration Options -- Testability Busses and ATE -- 11 Mechanical Guidelines -- Overall Test Philosophy -- Accessibility -- Connectors -- Board Layout Guidelines -- Adjustments -- Other Physical Guidelines -- 12 Surface Mount Technology Guidelines -- Mechanical Guidelines for SMT Board Design -- Electrical Guidelines for SMT Board Design -- 13 Software Guidelines -- Hardware Design Factors Required for Software Testability -- General Software Design Guidelines -- Specific Guidelines for Test Control -- Specific Guidelines for Test Modules -- Specific Guidelines for System Level Diagnostics -- Memory Tests -- Specific Guidelines for LRU Testing -- Test Software Development Plans -- 14 Testability Documentation -- Test Software Documentation -- Hardware Documentation -- 15 Implementation Guidelines -- Testability Program Flow -- Design Reviews -- Digital T-Score Rating System and Checklists -- 16 Test Techniques and Strategies -- Production Test Flows -- Cable, Backplane, and Bare Board Continuity Testing -- Loaded Board Opens and Shorts Testing -- In-Circuit Inspection Board Testing -- Manufacturing Defects Testing -- Digital Functional Testing -- Analog PCB Test Equipment -- Combinational Testers -- Choosing a Test Strategy -- Appendix A Testability Checklists -- Appendix B Digital T-Score Rating System