Wireless beyond the third generation -- Micro-operation cache -- L1 data cache decomposition -- Flow-based front-end throttling -- Power-aware high-performaance processors -- Adaptive bitwidth compression -- Variable voltage processors -- Dynamic voltage scheduling technique -- Hard real-time scheduling -- Low-energy flip-flops -- Clocked timing elements -- Low bit-rate wireless video -- Power-aware partitioned cache architectures -- Low-leakage dynamic multi-ported register file -- Energy-efficient load and store reuse -- Compiler suport for block buffering -- Automatic sources code specialization -- FV encoding -- Time-to-failure estimation for batteries -- Energy-efficient packet forwarding -- Energy aware communication systems -- Cooling and power considerations for semiconductors -- Asymmetric RF microsensor systems -- Leteral bipolar transistor -- Subsampling GSM receivers -- VTCMOS characteristics -- DRAM power management -- Run-time power estimation -- Fast, flexible, cycle-accurate anergy estimation -- Single edge-triggered & dual edge-triggered pulsed flip-flops -- Harmonic resonant rail driver -- Resonant clock generator -- Single-phase adiabatic systems -- Multi-threshol (MTCMOS) -- Variable well bias -- Ecodings for high-performance energy-efficien signaling -- Deep-submicron address buses -- Irredundant address bus encoding -- Self-organizing lists -- Wireless sensor networks -- Stack effect -- Leakage reduction -- Variable threshold voltage CMOS (VTCMOS) -- REverse body bias for leakage control -- Low-power high-performance nan0-scale circuit design -- Self-optimizing embedded microprocessor -- Low power pipelining of linear systems -- Datapath width optimization -- Superscalar processors -- Submicron CMOS for low power RF applications -- CMOS VCO architecture -- Low-power direct sewuence spread-spectrum modem architecture -- Tunable near-zero threshold CMOS -- Sub-1v dual-threshold domino circuit -- MT-DCVS circuit styles -- Selectively clocked skewed logic (SCSL) -- Compoler-directed dynamic voltage/frequency scheduling -- Variable voltage task scheduling algorithms -- Dual-Vth scheme -- Low-leakage PD-SOI circuits -- Mixed-swing logic -- Frequency-domain supply current macro-model -- Instantaneous compading -- Bias-circuit design of cascode operational amplifier -- Wide dynamic range operations -- Leakage current cancellation technique -- 176x144 self-clocked CMOS active pixel image sensor -- Cahed-code compression -- Gigabit ethernet 1000based transceivers -- Work reuse -- Clocking strategies -- Scannable latches -- Ultra-low power DLMS adaptive filter -- Dynamic-SDRAM-mode-control scheme -- Charge recycling -- VLSI interconnects -- Maximum voltage variation -- RLC models -- Lithium coin cell battery -- Power distribution network

Chulalinet's Book Delivery Request