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AuthorDesign Automation Conference (38th : 2001 : Las Vegas, NV)
TitleProceedings of the 38th design automation conference, Las Vegas Convention Center, Las Vegas, NV, June 18-22, 2001 / sponsored by ACM ... [et al.]
Imprint New York : ACM, 2001
Descript xxxiii, 868 p. ; 29 cm

CONTENT

Electronics industry supply chain -- Nanometer -- System-level configurability: bus, interface, and processor design -- Lotterybus -- Making verification more efficient -- SoC and high-level DFT -- Panel: the next HDL: if C++ is the answer, what was the question? -- Design for subwavelength manufacturability: impact on EDA -- New ideas in logic synthesis -- Analog design and modeling -- Scan-based testing -- Panel: your core-my problem? integration and verification of IP -- Configurable computing: reconfiguring the industry -- Interconnect design optimization -- Power estimation techniques -- Functional validation based on Boolean reasoning (BDD, SAT) -- Verification: life beyond algorithms -- Dissecting an embedded system: lessons from bluetooth -- Algorithmic and compiler transformations for high-level synthesis -- Gate delay calculation -- Memory, bus and current testing -- Panel: (when) will FPGAs kill ASIC's? -- Inductance 101 and beyond -- Memory optimization techniques for DSP processors -- Technology dependant logic synthesis -- Collaborative and distributed design frameworks -- Panel: when will the analog design flow catch up with digital methodology? -- Closing the gap between ASIC and custom: design examples -- Energy and flexibility driven scheduling -- Representation and optimization for digital arithmetic circuits -- Techniques for IP protection -- Visualization and animation for VLSI design -- Application-specific customization for systems-on-a-chip -- Satisfiability solvers and techniques -- Power and interconnect analysis -- Domain specific design methodologies -- Panel: debate: who has nanometer design under control? -- Analysis and implementation for embedded systems -- Industrial case studies in verification -- Integrated high-level synthesis based solutions -- Timing verification and simulation -- On-chip communication architectures -- Compiler and architecture interactions -- Timing with crosstalk -- Low power design: systems to interconnect -- Floorplanning representations and placement algoriths -- Panel: what drives EDA innovation? -- Signal integrity: avoidance and test techniques -- Novel approaches to microprocessor design and verification -- Scheduling techniques for power management -- Novel devices and yield optimization


Engineering design -- Data processing -- Congresses Computer-aided design -- Congresses

LOCATIONCALL#STATUS
Central Library (4th Floor)620.00420285 D457P 2001CHECK SHELVES

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