การทวนสอบวงจรอสมวารแบบควอไซดีเลย์อินเซนซิทีฟโดยซิกแนลทรานสิชันกราฟ / เด่นดวง ประดับสุวรรณ = Verification of quasi-delay-insensitive asynchronous circuits by the signal transition graph / Denduang Pradubsuwun
The circuit verification is a process to assure the correctness between the implemented circuit and its specification. This thesis proposes a design and development of the hierarchical verification process for Quasi-Delay-Insensitive (QDI) asynchronous circuits based on event-driven simulation. The complete verification process has two levels. First, we will verify each sub-circuit, with respect to its specification and then we will verify the whole circuit by considering only interconnected signals between sub-circuits. In each level of verification, we apply the test vector with event-driven simulation developed by Verilog in order to verify the asynchronicity of the circuit. The test vector is derived from the analysis of the Signal Transition Graph (STG) using various techniques including STG contraction, analysis of the concurrent temporal relation on STG based on input-output mode circuit's operation, and basis path testing. Moreover, we apply the timing-reliability evaluation of asynchronous circuittechnique to verify correctness of the QDI circuit's operation. Our approach is the smart simulation which is arranged in a semi-formal method. It can avoid the limitations of traditional verification methods. Experimemting with a set of benchmark circuits, the proposed approach shows high performance when measured by software metric i.e. cyclomatic complexity, which determines the number of test vectors. The results show a 21.08% reduction in numbers of all test vectors required for the first level of verification and an 87.81% reduction in numbers of all test vectors from the flat verification. In addition, our approach can also be carried out in a hierarchical structure. It also has other advantages such as reducing the complexity which is found in the whole circuit verification method, and quickly finding problems in the preliminary level without finish examining the whole circuit. Lastly, the verification results can be applied to similar sub-circuits without repeating the verification process
