This thesis proposes a method to design the Scalable-Delay-Insensitive (SDI) asynchronous combinational circuits. Asynchronous circuits are firstly divided into two circuit parts: dual-rail circuit and acknowledgement circuit. The dual-rail circuit processes the logical function, then the acknowledgement circuit verifies the stability of the whole circuit. With 2-rail encoding, the dual-rail circuit can be designed with the Inverter-free 2-rail logic implementation and Reduced-Ordered-Binary Decision Diagram (ROBDD) implementation while the acknowledgement circuit is designed from the analysis of signal propagation and the analysis of delay variation. To avoid using a C-element that enlarges the circuit, OR gates and buffers are used. Thus, the circuit can tolerate the maximum delay variation ratio. To compare the performance between the designed circuits and the Quasi-Delay-Insensitive (QDI) asynchronous combinational circuits, this research not only presents a method to measure the maximum delay variation ratio of the QDI circuits but also introduces a method to simulate the circuit operations with the maximum delay variation ratio and without the delay variation. From the experimental results, the SDI circuits have a lower hardware cost and perform faster than the QDI. The circuits in the input-output mode environment are better tolerant than in the fundamental mode. Eventually, the specification of the maximum delay variation ratio equals to the selections of environment operation models and the delay models of the circuit.
