Skipper: A Microarchitecture for Exploiting Control-Flow Independence -- Performance Characterization of a Hardware Mechanism for Dynamic Optimization -- Using Variable-MHz Microprocessors to Efficiently Handle Uncertainty in Real-Time Systems -- Design Space Evaluation of Grid Processor Architectures -- Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping -- Code Decompression Architecture for VLIW Processors -- Direct Load: Dependence-Linked Dataflow Resolution of Load Address and Cache Coordinate -- Reducing Power Repuirements of Instruction Scheduling through Dynamic Allocation of Multiple Datapath Resources -- Exploiting VLIW Schedule Slacks for Dynamic and Leakage Energy Reduction -- Reducing Power with Dynamic Critical Path Information -- Direct Addressed Caches for Reduced Power Consumption -- Modulo Schedule Buffers -- Graph-Partitioning Based Instruction Scheduling for Clustered Processors -- Modulo Scheduling with Integrated Register Spilling for Clustered VLIW Architectures -- Efficient Static Single Assignment Form form for Predication -- Impact of If-Conversion and Branch Prediction on Program Execution on the Intel@ Itanium Processor -- Mapping Reference Code to Irregular DSPs within the Retargetable, Optimizing Compiler COGEN(T) -- Select-Free Instruction Scheduling Logic -- Dual Use of Superscalar Datapath for Transient-Fault Detection and Recovery -- High-Speed Dynamic Instruction Scheduling Scheme for Superscalar Processors -- Reducing the Complexity of the File in Dynamic Superscalar Processors -- Saving Energy with Architectural and Frequency Adaptations for Multimedia Applications -- Enhancing Loop Buffering of Media and Telecommunications Applications using Low-Overhead Predication -- Cool-Cache for Hot Multimedia -- ZR: A 3D API Transparent Technology for Chunk Rendering -- Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution -- Dynamic Speculative Precomputation -- Heandling Long-Latency Loads in a Simultaneous Multithreading Processor -- Correctly Implementing Value Prediction in Microprocessors that Support Multithreading or Multiprocessing

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